𝐅𝐏𝐆𝔸𝐒𝐈𝐂

2022-08-30 13:54:02 Versatile list of HDL lint tools

https://airhdl.com/blog/2017/02/08/fpga-lint-tools/
(updated August 2022)

#lint #linter #sv #verilog #vhdl
@fpgasic Open / Comment

2022-07-27 13:06:09 openFPGALoader - Universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic, Cologne Chip). openFPGALoader works on Linux, Windows and macOS.

openFPGALoader just released version 0.9.0 with most notable evolutions:
libgpiod and XVC (XilinxInc Virtual Cable) support
ORBTrace mini (DFU) and tang Primer 20K support
GW2A, new Kintex models, ZynqMP Ultrascale (and Plus)

https://github.com/trabucayre/openFPGALoader/releases/tag/v0.9.0
https://trabucayre.github.io/openFPGALoader/

#jtag #loader #verilog #xvc #dfu #bitstream #ft2232
@fpgasic Open / Comment

2022-07-12 11:37:11 Verilog and SystemVerilog cheatsheet

#verilog #systemverilog #cheatsheet #digitaldesign
@fpgasic Open / Comment

2022-07-08 18:17:23 #fridaymeme
@fpgasic Open / Comment

2022-07-07 22:39:01 svinst - tool takes a SystemVerilog file as input and produces as output the module(s) declared in that file, along with the module(s) instantiated in each one of those module declarations (written in Rust).

https://github.com/sgherbst/svinst

#parser #parsing #instantiation #sv #systemverilog #rust
@fpgasic Open / Comment

2022-07-05 18:40:45 BENDER - a dependency management tool for hardware design projects written in Rust.

It provides a way to define dependencies among IPs, execute unit tests, and verify that the source files are valid input for various simulation and synthesis tools.

Principles
Be as opt-in as possible
Allow for reproducible builds
Collect source files
Manage dependencies
Generate tool scripts

https://github.com/pulp-platform/bender
https://pulp-platform.org/docs/riscv_workshop_zurich/bender_wosh2019.pdf

#build #buildsystem #makefile #bender #ip #dependencies #scripts #rust
@fpgasic Open / Comment

2022-06-29 14:56:01 sv-parser - SystemVerilog parser library fully compliant with IEEE 1800-2017 written in Rust

https://github.com/dalance/sv-parser

#parser #lexer #sv #systemverilog #rust
@fpgasic Open / Comment

2022-06-27 12:51:01 SVUnit - an open-source test framework for ASIC and FPGA developers writing Verilog and SystemVerilog code.

SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates.

https://github.com/svunit/svunit
http://www.agilesoc.com/svunit

#test #testbench #verification #sv #systemverilog #svunit
@fpgasic Open / Comment

2022-06-23 14:37:27 svlint - awesome SystemVerilog linter written in Rust

https://github.com/dalance/svlint
https://github.com/dpretet/dotfiles/blob/master/svlint.toml

#lint #linter #sv #systemverilog #rust
@fpgasic Open / Comment

2022-01-10 10:30:01 Have you ever wondered how to explain the difference between FPGA and CPU?

CPU vs FPGA

@fpgasic Open / Comment