★𝗜𝗣𝕔𝕠𝕣𝕖𝕤★

2021-03-30 18:24:32 Verilog LFSR - Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation.

lfsr.v - Parametrizable combinatorial LFSR/CRC module
lfsr_crc.v - Parametrizable CRC computation wrapper
lfsr_descramble.v - Parametrizable LFSR self-synchronizing descrambler
lfsr_prbs_check.v - Parametrizable PRBS checker wrapper
lfsr_prbs_gen.v - Parametrizable PRBS generator wrapper
lfsr_scramble.v - Parametrizable LFSR self-synchronizing scrambler

Links:
Sources

#verilog #python #MyHDL #LFSR #CRC
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2021-03-03 18:01:17 GLIP - The Generic Logic Interfacing Project.

GLIP is a solution for transferring data through FIFOs between a host, usually a PC, and a target, usually a hardware component such as an FPGA or a microcontroller. The actual data transport can happen through various interfaces, such as USB 2.0, JTAG or TCP.

Features
Easy FIFO-based communication, abstracting away all low-level details
Support for different communication channels through backends
Side-channel communication (e.g. reset signals)
Developed on and for Linux

Links:
Documentation
Sources

#verilog #SV #JTAG #FIFO #USB
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