S-Link - a lightweight chiplet/chip-to-chip controller. S-Link is a simple, scalable, and flexible link controller protocol geared towards chiplets and chip-to-chip communication.
S-Link defines the link layer, and gives freedom for various application and physical layers. The ultimate goal of S-Link is to provide a simple alternative for chiplet communication compared to other protocols.
Features:
Mult-lane support (upto 128+)
128b/130b encoding
Parameterizable Application Data Widths
Configurable Attributes for fine tuning link controls and/or active link management
ECC/CRC for error checking of packet headers and payload data
Parameterizable pipeline stages to optimize for frequency and/or power
https://github.com/waviousllc/wav-slink-hw
#chiplet #protocol #verilog
@ipcores
