𝐅𝐏𝐆𝔸𝐒𝐈𝐂

2021-03-31 10:12:01 pysv - a lightweight Python library that allows functional models to be written in Python and then executed inside standard SystemVerilog simulators, via DPI.

Supported Simulators
Cadence Xcelium
Synopsys VCS
Mentor Questa
Vivado Simulator
Verilator


https://github.com/Kuree/pysv

#SV #systemverilog #python #simulation #cosimulation
@fpgasic Open / Comment

2021-03-30 18:48:30 OpenRAM - an Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.

https://github.com/VLSIDA/OpenRAM

#ASIC #verilog #python #memory #SRAM #generator #GDS #netlist #netgen #magic #Ngspice
@fpgasic Open / Comment

2021-02-23 10:10:07 Dockerize Synopsys/Cadence EDA tools - is the Dockerfiles to dockerize popular EDA tools.

With docker images we could do:

Build/test your design on the cloud server
Maintain tools with as many different version as you want without issues
Provide tools for you or your peer's desktop computer regardless of which kind of Linux you are using
Continuous Integration (CI)

https://github.com/limerainne/Dockerize-EDA

#docker #cadence #synopsys #eda
@fpgasic Open / Comment

2021-02-22 12:56:01 Verilog-HDL/SystemVerilog/Bluespec support for VS Code

Features
Syntax Highlighting
◦ Verilog
◦ SystemVerilog
◦ Bluespec SystemVerilog
◦ Vivado UCF constraints
◦ Synopsys Design Constraints
Simple Snippets
Linting support from:
◦ Icarus Verilog
◦ Vivado Simulation
◦ Modelsim
◦ Verilator
Ctags Integration
◦ Autocomplete
◦ Document Symbols Outline
◦ Hover over variable declaration
◦ Go to Definition & Peek Definition
◦ Module Instantiation

https://github.com/mshr-h/vscode-verilog-hdl-support

#VScode #MS #verilog #SV #bluespec #lint snippets #syntax #icarus #modelsim #verilator
@fpgasic Open / Comment

2021-02-17 17:33:45 fp2p - FPGA Port To Pin tool.

Utility for safe and reusable port to pin assignment in multi-board FPGA designs.

The implementation has two main goals, safety (check as many potential human mistakes as possible) and reusability (reuse connections mappings, defined in files, in multiple designs). It is fully declarative and programming language-agnostic from the users perspective.

https://github.com/m-kru/fp2p

#FPGA #pinout #pin #multiboard #python
@fpgasic Open / Comment

2021-02-16 14:35:01 IEEE P1735 decryptor for VHDL

This tool allow to recover full source code of encrypted module (provided you have an extracted private key from the software you're using). Usually software vendors do not care much about hiding their private keys. The decryption is done in two stages:

using the private key, a session key is decrypted using RSA decryption procedure
data block is decoded using this session key and AES-128-CBC decryption procedure

https://github.com/dmitrodem/p1735_decryptor

#decryptor #python #IP #VHDL #P1735 #encryption #protection #Aldec
@fpgasic Open / Comment

2021-01-19 13:08:48 [WiP] ligeia - replacement for GTKWave, written in Rust with high-performance and larger-than-memory traces in mind.

https://github.com/lachlansneff/ligeia

#rust #VCD #dump #GTKWave
@fpgasic Open / Comment

2021-01-15 22:36:53 HDElk - a web-based HDL diagramming tool. It was designed to permit the easy visual representation of Verilog or VHDL (generically HDL’s, Hardware Description Languages) in web pages by creation of simple javascript specification objects.

Links:
Doc
Src

#HDL #documentation #javascript #js #diagram #authoring Open / Comment

2021-01-14 00:15:01 PyVCD - package writes Value Change Dump (VCD) files as specified in IEEE 1364-2005.
This tool also can generate GTKWave save files.

doc
src

#python #VCD #dump #GTKWave Open / Comment

2020-10-27 12:59:33 Intel PSG is providing series of online training.
Due to COVID-19 these training is FREE!
It's live (nor recorded) training with instructors.
Get your advanced skills and your new possibilities!

https://www.intel.com/content/www/us/en/programmable/support/training/schedule.html

#Intel #onlinetraining #webinar #training #FPGA #Quartus #STA #HLS #OneAPI #PlatformDesigner Open / Comment